Electronic systems and circuits have made a significant contribution towards the advancement of modern society and are utilized in a number of applications to achieve advantageous results. Electronic technologies such as digital computers, calculators, audio devices, video equipment, and telephone systems have facilitated increased productivity and reduced costs in analyzing and communicating data, ideas and trends in most areas of business, science, education and entertainment. Correspondingly, as technology has advanced, electronic technologies are increasingly shrinking in size. As electronic components shrink, electrical interference and other negative effects on electrical components, such as wires, have an increasingly large impact. The tiny widths and close proximity of adjacent bitlines introduces resistance and capacitance (RC) delays that can hinder chip performance.
FIG. 1 shows a cross section of a conventional configuration of global bitlines of a semiconductor device 100. Each of bitlines 102-110 are within layer 101 and are separated by a fixed spacing 116. Bitlines 102-110 further have a uniform width 114. The width of each of the bitlines has an impact on the resistance of the bitline.
The characteristic of a bitline configuration is known as pitch which is the width of the bitline and the spacing between that bitline plus the adjacent bitline. The pitch is thus shown by distance 112. Conventionally, the pitch is fixed based on the semiconductor manufacturing process, such as 90 mm. The fixing of the pitch has thus limited conventional solutions to making changes to the spacing between the bitlines or changing the width of the bitlines.
Unfortunately, the fixed nature of the pitch also results in a constant RC delay making changes to the width or spacing ineffective in changing the RC delay. For example, when the width is increased, thereby reducing the resistance, the reduced spacing results in an increase in capacitance. Similarly, when the spacing is increased, thereby reducing the capacitance, the reduced width results in an increased resistance.
The capacitance portion of the RC delay may be expressed by the equation:
  C  =      K    ⁢                  ⁢          ɛ      0        ⁢          A      D      Where A is the area, D is the distance between bitlines, K is the dielectric constant of the material, and ∈0 is the permittivity of free space. The area (A) and thickness (D) are governed by the microelectronic chip size.
Conventional solutions have been focused on using materials which have a low dielectric constant. Unfortunately, the use of new materials is expensive because it requires new equipment, new tools, and achieving a yield matching previous methods and materials is increasingly difficult.
Accordingly, what is needed is a bitline configuration which overcomes the RC delay of conventional designs to allow semiconductor devices to be made smaller.